The present invention relates generally to logic circuits of the type fabricated on a monolithic semiconductor chip employing insulated-gate field-effect transistors (IGFETs) and, more particularly, to a D-type latch which can be fabricated employing complementary metal-oxide-semiconductor (CMOS) transistor technology.
As is known, a D-type latch is a form of latch useful in digital logic applications. A D-type latch has a single data input (D input), a pair of complementary data outputs (Q and Q), and a clock input, which is also referred to in the art as an enable input. In operation, when the latch is enabled (for example, with the clock or enable input at a logic "high" level, also known as binary "1"), data in the form of a logic level present at the data input (D input) is transferred to the data output (Q output), with complementary data available at the complementary data output (Q). So long as the latch remains enabled (with the clock or enable input high in this example), the Q and Q outputs follow the data input, with the Q output always being the complement of the Q output. When the clock or enable input transitions to the state where the latch is not enabled (in this example, a clock high to low transition), the logic level present at the input just prior to the clock transition is retained, regardless of subsequent changes in the data input, until such time as the latch is again enabled.
Typically, a plurality of such latches are included in a single integrated circuit. In one form, such latches are available in packages of, for example, four latch circuits formed on a monolithic silicon semiconductor chip and included in a single integrated circuit package. An example of such an integrated circuit, commercially available, is an RCA Type No. CD4042 "COS/MOS Quad Clocked D Latch". In another form, such latches may be included as but a small part of a much larger integrated circuit (e.g. large scale integration), in combination with either a variety of other types of digital logic elements and circuits comprising a functional device, or in combination with a multiplicity of other D-type latches comprising a D-type latch array organized much like a semiconductor memory array.
In either case, the integrated circuit typically includes a number of other elements supporting the latch circuit. These other elements include at least voltage supply lines or nodes. Also, typical D-type latch circuits require complementary clock inputs (e.g. CLK and CLK), and an inverter will typically be included, common to a number of individual D-type latch circuits, to provide the complementary CLK and CLK signals.
In one common circuit application, D-type latches are arranged in pairs to respectively comprise the master section and the slave section of an edge-triggered D-type flip-flop, useful either as an individual digital logic circuit element, or connected in series with a plurality of other edge-triggered D-type flip-flops to form a clocked shift register. In an edge-triggered D-type flip-flop, the master section and the slave section are connected in series, with the clock inputs oppositely connected such that one latch section is enabled while the other is disabled, and vice-versa. Typically, for a logic low clock input, the master section is enabled and input data enters the master section. When the clock input goes high, the master section is disabled, isolating the flip-flop input, and the slave section is enabled, allowing data to be transferred from the master section to the slave section, and thus to the flip-flop output An example of a commercially available edge-triggered D-type flip-flop including a pair of D-type latches in a master/slave configuration is an RCA Type No. CD4013 "Dual `D`-Type Flip-Flop". Examples of commercially-available static shift registers including a plurality of D-type flip-flops as individual stages are an RCA Type No. CD4015, "COS/MOS Dual 4-Stage Static Shift Register", and an RCA Type No. CD4006 "COS/MOS 18-Stage Static Shift Register".
In the design of integrated circuits, particularly large scale integrated circuits comprising a multiplicity of individual logic elements, important considerations are minimizing the transistor count and reducing the circuit area required for each individual logic element or circuit.
Typical prior art D-type static latch circuits, when implemented in CMOS, generally comprise at least a pair of CMOS inverters cross-coupled in a latching configuration and a pair of CMOS transmission gates for selectively electrically connecting the inverter inputs and outputs to appropriate circuit nodes. The transmission gates are selectively enabled by the complementary clock inputs CLK and CLK. For example, an RCA Type No. CD4042 D-type latch includes one transmission gate between the latch input and the input of one inverter, another inverter cross-coupled with the one inverter, and another transmission gate in series with the other inverter output. Since a CMOS transmission gate and a CMOS inverter each require two IGFETs, the overall latch having two inverters and two transmission gates includes at least eight transistors. Various other D-type latch circuits require larger numbers of transistors.
Also relevant in the context of the present invention are modified CMOS inverter circuits capable of being selectively enabled, such as are disclosed in Heuner et al U.S. Pat. No. 3,716,723 and Parrish et al U.S. Pat. No. 3,716,724. A standard CMOS inverter includes a P-channel IGFET having its source connected to +V.sub.DD and an N-channel IGFET having its source connected to ground. The two IGFET drains are connected together and to the inverter output. The two IGFET gates are connected together and to the inverter input. Thus, for a logic low input, the P-channel IGFET is turned on and pulls the output to +V.sub.DD (logic high), while the N-channel IGFET is off. For a logic high input, the N-channel IGFET is turned on, pulling the output to ground (logic low), while the N-channel IGFET is off. For selective enablement, the modified inverters of the above-referenced Heuner et al and Parrish et al U.S. Pat. Nos. 3,716,723 and 3,716,724 include an isolation diode connected in series with the channel of each of the IGFETs, and the inverters are powered from the CLK and CLK lines, rather than from +V.sub.DD and ground. For one set of CLK and CLK logic voltage levels, e.g. with CLK high and CLK low, either diode may be forward-biased, and the inverter is enabled. For a complementary set of CLK and CLK logic voltage levels, e.g. with CLK low and CLK high, both diodes are always reverse-biased, and the inverter is disabled. When such an inverter is disabled, its output impedance is quite high, to the extent that the inverter output is essentially an open circuit with respect to either logic voltage level. Such inverters capable of being selectively enabled can be configured as static and dynamic shift register stages which avoid the use of transmission gates, as is also disclosed in the above-referenced Heuner et al and Parrish et al U.S. Pat. Nos. 3,716,723 and 3,716,724.